1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a nonvolatile semiconductor memory device capable of compensating for a change of a bit-line precharge level due to temperature change.
2. Description of the Related Art
In A nonvolatile semiconductor memory device, word lines and bit lines are arranged in a matrix of rows and columns, respectively, and memory cells are positioned at the intersections of these rows and columns. The word line is selected by a row address, and the bit line is selected by a column address. Data in the memory cell at a selected position is read through an input and output circuit.
As an example of a nonvolatile semiconductor memory device, a NAND flash memory device has a basic structure consisting of a string of a plurality of memory cells connected to a bit line, and a block of which a plurality of these strings share one contact.
The nonvolatile semiconductor memory device is configured to include a memory cell array, a page buffer and the like. The memory cell array is comprised of the blocks having a plurality of strings as a basic unit. Each string includes a plurality of memory cells serially connected. Each of the memory cells has a floating gate and a control gate, and electrically performs program and erase operations by accumulating electrons in the floating gate or discharging the accumulated electrons, respectively. A memory cell with accumulated electrons in its floating gate is called a “programmed cell”, and a memory cell from which electrons are discharged from its floating gate is called an “erased cell”.
The program and erase operations of the nonvolatile semiconductor memory device use an F-N tunneling phenomenon. The threshold voltage of a cell transistor depends on whether or not electrons are injected into the floating gate or electrons are discharged from the floating gate. An erased cell acquires a negative threshold voltage (for example, −3V) by discharging electrons from the floating gate to a bulk, a source or a drain. In this instance, the erased cell is called an “on cell”. A programmed cell has a positive threshold voltage (for example, +1V) acquired by injecting electrons into the floating gate. At this time, the programmed cell is called an “off cell”.
In order to confirm whether or not the memory cell is a programmed cell or an erased cell, a read voltage V read (for example, +4.5V) is applied to non-selected word lines, and 0V is applied to a selected word line. This is called a “reading operation”. Before the reading operation is performed, a bit line precharging process needs to occur. When the bit line is precharged, the bit line has a specific precharge level. After the bit line is precharged the reading operation can take place. At this time, if the memory cell connected to the selected word line is an erased cell, the precharge level of the bit line decreases. However, if the memory cell is a programmed cell, the precharge level of the bit line is maintained. Thus, the reading operation determines whether the memory cell is an erased cell or a programmed cell.
To precharge the bit line, a transistor characteristic known as “shut-off” is used, explained as follows. In an NMOS transistor, which includes a drain (D), a source (S), and a gate (G), a power supply voltage (Vcc) is applied to the drain (D). Let the gate-source voltage be expressed as VGS, and the gate voltage be expressed as VG. Then the voltage precharged to the source (S) is VG−VTH, being determined by VGS−VTH. When VGS>VTH, the NMOS transistor is turned-on, and the source (S) is precharged. But if the level of the source (S) is VGS−VTH or more, the NMOS transistor is turned-off. This characteristic of the NMOS transistor is called “shut-off”. Accordingly, the bit line has the precharge level determined by VGS−VTH due to the shut-off characteristic of the transistor.
The precharge level VG−VTH of the bit line is influenced by the threshold voltage of the transistor due to the shut-off characteristic. That is, if the threshold voltage rises, the precharge level of the bit line drops, and if the threshold voltage drops, the precharge level of the bit line rises. The transistor's threshold voltage changes, however, with changing temperature. Generally, the threshold voltage decreases by about 2 mV per 1° C. temperature rise. Accordingly, if the temperature varies, the precharge level of the bit line varies. If the temperature increases then the threshold voltage decreases, causing the precharge level of the bit line to increase. Similarly, if the temperature decreases, then the threshold voltage increases, causing the precharge level of the bit line to decrease. This is a drawback because a memory cell sensed as an on cell at a high temperature may be erroneously sensed as an off cell at a low temperature.